1 tp2635/tp2640 features low threshold -2.0v max. high input impedance low input capacitance fast switching speeds low on resistance free from secondary breakdown low input and output leakage complementary n- and p-channel devices applications logic level interfaces C ideal for ttl and cmos solid state relays battery operated systems photo voltaic drives analog switches general purpose line drivers telecom switches ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? general description these low threshold enhancement-mode (normally-off) transistors utilize a vertical dmos structure and supertexs well-proven silicon-gate manufacturing process. this combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coef? cient inherent in mos devices. characteristic of all mos structures, these devices are free from thermal runaway and thermally induced secondary breakdown. supertexs vertical dmos fets are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. ordering information device package options bv dss /bv dgs r ds(on) (max) v gs(th) (max) i d(on) (min) so-8 to-92 tp2635 - tp2635n3 -350v 15 -2.0v -0.7a - tp2635n3-g tp2640 tp2640lg tp2640n3 -400v 15 -2.0v -0.7a TP2640LG-G tp2640n3-g -g indicates package is rohs compliant (green) absolute maximum ratings parameter value drain to source voltage bv dss drain to gate voltage bv dgs gate to source voltage 20v operating and storage temperature -55c to +150c soldering temperature 1 +300c absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. note 1 . distance of 1.6mm from case for 10 seconds. pin con? gurations s g d to-92 1 2 3 4 8 7 6 5 so-8 (top view) nc nc s g d d d d p- channel enhancement-mode vertical dmos fets
2 tp2635/tp2640 electrical characteristics (t j = 25c unless otherwise speci? ed) symbol parameter min typ max units conditions bv dss drain-to-source break- down voltage tp2640 -400 -- vv gs = 0v, i d = -2.0ma tp2635 -350 v gs(th) gate threshold voltage -0.8 - -2.0 v v gs = v ds , i d = -1.0ma v gs(th) change in v gs(th) with temperature - - 5 mv/ o cv gs = v ds , i d = -1.0ma i gss gate body leakage - -100 na v gs = 20v, v ds = 0v i dss zero gate voltage drain current - - -1.0 a v ds = -100v, v gs = 0v -10.0 a v ds = max rating, v gs = 0v -1.0 ma v ds = 0.8 max rating, v gs = 0v, t a = 125 o c i d(on) on-state drain current 0.7 - - a v gs = -10v, v ds = -25v r ds(on) static drain-to-source on-state resistance - 12 15 v gs = -2.5v, i d = -200ma 11 15 v gs = -4.5v, i d = -150ma 11 15 v gs = -10v, i d = -300ma r ds(on) change in r ds(on) with temperature - - 0.75 %/ o cv gs = -10v, i d = -300ma g fs forward transconductance 200 - - m v ds = -25v, i d = -300ma c iss input capacitance - - 300 pf v gs = 0v, v ds = -25v, f = 1mhz c oss common source output capacitance - - 50 c rss reverse transfer capacitance - - 12 t d(on) turn-on delay time - - 10 ns v dd = 25v, i d = 2.0a, r gen = 25? t r rise time - - 15 t d(off) turn-off delay time - - 60 t f fall time - - 40 v sd diode forward voltage drop - - -1.8 v v gs = 0v, i sd = 200ma t rr reverse recovery time - 300 - ns v gs = 0v, i sd = 1.0a notes: 1.all d.c. parameters 100% tested at 25c unless otherwise stated. (pulse test: 300s pulse, 2% duty cycle.) 2.all a.c. parameters sample tested. n- channel switching waveforms and test circuit thermal characteristics package i d (continuous) 1 i d (pulsed) power dissipation @t c = 25 o c jc ( o c/w) jc ( o c/w) i dr 1 i drm so-8 -210ma -1.25a 1.3w 2 24 96 2 210ma -1.25a to-92 -180ma -0.8a 1.0w 125 170 -180ma -0.8a notes: 1. i d (continuous) is limited by max rated t j . 2. mounted on fr4 board, 25mm x 25mm x 1.57mm 90% 10% 90% 90% 10% 10% pulse generator v dd r l output d.u.t. t (on) t d(on) t (off) t d(off) t f t r input input output 0v v dd r gen 0v -10v
3 tp2635/tp2640 typical performance curves output characteristics -2.0 -1.6 -1.2 -0.8 -0.4 0 v ds (volts) i ) s e r e p m a ( d saturation characteristics v ds (volts) i ) s e r e p m a ( d maximum rated safe operating area -1 -1000 -100 -10 -10 -1.0 -0.1 -0.01 -0.001 v ds (volts) i ) s e r e p m a ( d thermal response characteristics ) d e z i l a m r o n ( e c n a t s i s e r l a m r e h t 1.0 0.8 0.6 0.4 0.2 0 0.001 10 0.01 0.1 1.0 t p (seconds) transconductance vs. drain current 1.0 0.8 0.6 0.4 0.2 0 0 -0.8 -0.4 g s f ) s n e m e i s ( i d (amperes) power dissipation vs. temperature 0150 100 50 2.0 1.6 1.2 0.8 0.4 0 125 75 25 t c c) ( d p ) s t t a w ( to-92 t c = 25 c p d = 1.0w so-8 to-92 t a = -55 c v ds = -25v 0 -10 -20 -30 -50 -40 0 -2 -4 -6 -10 -8 25 c 125 c -1.2 -2.0 -1.6 -1.0 -0.8 -0.6 -0.4 -0.2 0 v gs = -10v -3v -4v -6v -8v v gs = -10v -8v -6v -3v -4v so-8 (pulsed) t c = 25 c to-92 (dc) to-92 (pulsed) so-8 (dc)
4 tp2635/tp2640 typical performance curves (cont.) gate drive dynamic characteristics q (nanocoulombs) g v s g ) s t l o v ( t j ) h t ( s g v) d e z i l a m r o n ( ) n o ( s d r) d e z i l a m r o n ( v th and r ds variation with temperature c) ( on-resistance vs. drain current (amperes) d ) s m h o ( ) n o ( s d r variation with temperature dss s s d ) d e z i l a m r o n ( v b c) ( t j transfer characteristics v gs (volts) i ) s e r e p m a ( d capacitance vs. drain-to-source voltage 400 ) s d a r a f o c i p ( c v ds (volts) i bv 0 -10 -20 -30 -40 200 300 100 0 0 -2-4-6-8-10 -2.0 -1.6 -1.2 -0.8 -0.4 0 -50 0 50 100 150 1.1 1.0 30 24 18 12 6 0 1.2 1.0 0.8 0.6 0.4 -10 -8 -6 -4 -2 012 3 45 -50 0 50 100 150 263pf v ds = -10v v ds = -40v 678pf v gs = -4.5v v gs = -10v v gs = -2.5v +12 5 c 0 -0.4 -0.8 -1.2 -2.0 -1.6 f = 1mhz c iss c oss c rss 0.9 2.5 2.0 1.5 1.0 0.5 0 r ds(on) @ -10v, -0.3a 25 c t a = -55 c v ds = -25v 0 v (th) @ -1ma
5 tp2635/tp2640 (the package drawing(s) in this data sheet may not re? ect the most current speci? cations. for the latest package outline information go to http://www.supertex.com/packaging.html .) 8-lead soic package outline (lg) 45 5 - 15 (4 plcs) 4.90 0.10 1.27bsc 6.00 0.20 3.90 0.10 notes: 1. all dimensions in millimeters. angles in degrees. 2. if the corner is not chamfered, then a pin 1 identifier must be located within the area indicated. note 2 1.75 max 0.10 - 0.25 0.31 - 0.51 1.25 min 0.25 - 0.50 0 - 8 0.40 - 1.27 0.17 - 0.25 top view side view end view note 2 1 8 3-lead to-92 package outline (n3) 1 2 3 seating plane 1 2 3 front view 0.175 - 0.205 0.170 - 0.210 0.500 min 0.014 - 0.022 0.045 - 0.055 0.095 - 0.105 0.125 - 0.165 0.135 min 0.080 - 0.105 0.014 - 0.022 side view bottom view notes: all dimensions are in millimeters; all angles in degrees. doc.# dsfp-tp2635_tp2640 c032807
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